Research

I am a early-stage researcher and PhD student integrated in the HPCAS group at INESC-ID and the Cyberphysical Computing Group at INESC INOV-Labs.

You can take a look into my public research profiles below:

As of now I am a member of the SMARTCHIP project, which has the objective to design a Low-Power System for Embedded AI workloads, while being able to be reconfigured for different networks.

This accelerator+CPU system is being prototyped in FPGA and will be tapped out to as an ASIC in a later stage.

This project is supervised by Prof. Horácio Neto, Prof. Mário Véstias, Prof. José Teixeira de Sousa, Prof. Rui Policarpo Duarte, and Prof. João Vaz.

Research Interests and Applications

My main insterest are related to Digital System Design, Reconfigurable Computing, and Computer Architectures, spanning from

among others.

As for the principal applications of my research, I would highlight:

and overall making edge computing more efficient and feasible.

Selected Publications

João Barreiros Rodrigues, Horácio C. Neto, and Mário Véstias. 2026. ARES: Dataflow Co-Design for Embedded Swin Transformer Acceleration on SoC- FPGAs. In Proceedings of the 16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2026) [ACCEPTED]